Particular embodiments generally relate to phase lock loops (PLLs). Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
FIG. 1a discloses an example of a PLL 100. PLL 100 may be part of a transceiver that transmits/receives a radio frequency signal. PLL 100 generates a local oscillator (LO) signal that is used in upconversion or downconversion of a radio frequency signal in a transceiver. PLL 100 includes a crystal oscillator 102 (TCXO) configured to generate a reference clock signal. TCXO 102 may be an external component to a chip including PLL 100. Reference clock buffers 104 buffer the reference clock signal and output the signal to a phase frequency detector 106. Phase frequency detector 106 compares a phase difference between the clock signal and a feedback signal received in a feedback loop. Frequency detector 106 outputs a signal that represents the difference in phase between the two input signals.
A charge pump 108 and a loop filter 110 convert the phase information output by phase frequency detector 106 into a voltage or current. For example, a tuning voltage Vtune is a control signal input into a radio frequency voltage controlled oscillator (RF VCO). RF VCO generates a sinusoidal signal with a frequency controlled by tuning voltage Vtune. RF buffers 114 then output the RF signal generated by the RF VCO.
The sinusoidal signal output by RF VCO 112 is also fed back into an integer frequency divider 116. A sigma-delta (SD) modulator 118 and integer frequency divider 116 provide non-integer frequency division capability. A fractional average division factor may be achieved. The phase of the signal output by integer frequency divider 116 is compared with the phase from the input reference signal. The comparison is used to adjust the RF VCO frequency to keep phase lock.
Fractional spurs may be generated in PLL 100. Two main mechanisms may cause the generation. For example, a fractional spur may be generated due to sigma-delta modulator quantization noise combined with non-linearity of the PLL loop. A sigma-delta modulator may be used to drive the integer frequency divider division factor to obtain a fractional average division factor, which may introduce noise into PLL 100. Non-linearity of several blocks in PLL 100, such as integer frequency divider 116, phase frequency detector 106, and charge pump 108 may cause generation of fractional spurs.
Fractional spurs may also be generated by sub-sampling of a radio frequency (RF) carrier (RF attacker) by blocks of PLL 100 working at the reference frequency Fref. For example, frequency divider 116, phase frequency detector 106, charge pump 108, and reference clock buffers 104 are usually sensitive digital circuits clocked at reference frequency Fref. These blocks sub-sample the RF attacker and convert the RF attacker to baseband as a fractional spur. These spurs may be considered dominant in PLL 100. The spurs may be generated from RF attackers at the local oscillation (LO) frequency and the multiple/sub-multiples of the LO frequency.
FIG. 1b shows an example of the spectrum of the RF carrier generated by PLL 100, featuring phase noise and fractional spurs. At 120, an RF carrier is shown at the local oscillating frequency flo. At 122, phase noise is shown. Fractional spurs are shown at 124. The fractional /spurs are generated at an offset Δf from the RF carrier. If the offset Δf is smaller than the PLL bandwidth, the fractional spurs are not filtered by PLL 100 and can degrade the RF carrier spectrum and also system performance. A spectral emission mask can be violated in the transmitter because the baseband spectrum is up-converted around the fractional spurs. Also, reception in the presence of strong interferers (blockers) can be compromised in the receiver because fractional spurs down-convert the interferer to baseband.
FIG. 1c shows an example of the generation of fractional spurs. An RF attacker may be any RF carrier in the system that may result in spurious tones. RF attackers may be the RF signals distributed by RF VCO 112 and RF buffers 114 across a chip that includes the transmitter/receiver. The RF attackers may couple to blocks of PLL 100 that are implemented as digital circuits that are clocked at reference frequency Fref. These blocks are typically reference clock buffers 104, phase frequency detectors 106, charge pump 108, and frequency divider 116. Coupling may occur in different ways, such as substrate coupling, ground/supply coupling, magnetic coupling, etc.
If an RF attacker is superimposed on a clock signal of a frequency Fref, and this clock signal drives an edge-sensitive digital circuit, the RF attacker undergoes sub-sampling. The resulting signal is affected by jitter and may feature two sidebands at Δf from the clock signal fundamental frequency Fref. FIG. 1d shows the effects of an RF attacker. For example, at 126, an RF attacker 128 is superimposed on a clock signal 120. After clock signal 120 is input into an edge-sensitive digital block 130, jitter 132 appears on clock signal 120. For example, sidebands 136 result at Δf from clock signal 120 fundamental frequency. Sidebands 136 are transferred at the output of PLL 100 as sidebands at Δf around the RF carrier frequency flo, which are referred to as fractional spurs. Because the fractional spurs are amplified by PLL feedback division factor (>>1), even a small RF attacker can cause spurious tones to appear at the RF output. For example, at 134, an RF attacker is shown at frequency frf=kFref+Δf, where k is an integer. At 136, the fractional spurs are shown at the output as +/−Δf sidebands around the clock signal frequency Fref. These fractional spurs are then amplified by the PLL as +/−Δf sidebands 136 around the RF carrier frequency flo.